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40 v, 200 ma, low noise, cmos ldo preliminary technical data ADP7142 features low noise: 1 1 vrms independent of fixed output voltage psrr of 8 3 db @ 10 khz, 68 db @ 100 khz, 5 0 db @ 1 mhz, v out 5v, v in = 7v input voltage range: 2.7 v to 40 v maximum output current: 200 ma low dropout voltage: 200 mv @ 200 ma load, v out = 5v initial accuracy: 1% accuracy over line, load, and temperature: 2% user programmable soft start (lfcsp and soic only) low quiescent current, i gnd = 5 0 a with no load low shutdown current: 1.5 a @ v in = 5 v, 3a @ v in = 40 v stable with small 2.2f ceramic output capacitor 16 fixed output voltage options: 1.2v to 5.0v adjustable output from 1 .2 v to v in - v do output may be adjusted above initial set point precision enable 2x2mm, 6 - lead lfcsp package, 8 - lead soic, 5 - lead tsot applications regulation t o noise sensitive applications: adc, dac circuits, precision amplifiers , power for vco vtun e control communications and infrastructure medical and healthcare industrial and instrumentation typical application circuit s vout = 5 v vin = 6 v vout vin gnd en 2 . 2 uf cin 2 . 2 uf cout on off sense / adj 1 nf css ss figure 1 . ADP7142 with fixed output voltage, 5 v 2k 10k vout=6v vin=7v vout vin gnd en 2.2uf cin 2.2uf cout on off sense/adj 1nf css ss figure 2 . ADP7142 with 5v output adjusted to 6 v general description the ADP7142 is a cmos, low dropout linear regulator that operates from 2.7 v to 40 v and provide up to 200 ma of outpu t current. these high input voltage ldos are ideal for regulation of high performance analog and mixed signal circuits operating from 40 v down to 1.2 v rails. using an advanced proprietary architecture, they provide high power supply rejection, low noise , and achieve excellent line and load transient response with just a small 2.2 f ceramic output capacitor. the ADP7142 is available in 16 fixed output voltage options. each fixed output voltage may be adjusted above the initial set point with an external feedback divider. this allows the ADP7142 to provide an output voltage from 1.2 v to vout - v do with high psrr and low noise. user programmable soft start with an external capacitor is available in the lfcsp and soic packages. the ADP7142 regulator output noise is 11 vrms independent of the output voltage for the fixed options of 5v or less. the ADP7142 is available in a 6 - lead, 2 mm 2 mm lfcsp making them not only very compact solutions, but also providing excellent thermal performance for application s requiring up to 200 ma of output current in a small, low - profile footprint . the ADP7142 is also available in a 5 - lead tsot and an 8 - lead soic. rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2014 analog devices, inc. all rights reserved. free datasheet http://
ADP7142 preliminary technical data table of contents features .......................................................................................... 1 applications ....................................................................................... 1 regulation to noise sensitive applications: adc, dac circuits, precision amplifiers, power for vco vtune control ................... 1 communications and infrastructure ............................................. 1 medical and healthcare ................................................................... 1 industrial and instr umentation ...................................................... 1 typical application circuits ........................................................... 1 general description ......................................................................... 1 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution ...................................................................................5 pin configurations and function descriptions ............................6 typical performance characteristics ..............................................8 theory of operatio n ...................................................................... 14 applications information .............................................................. 15 capacitor selection .................................................................... 15 programa ble precision enable ..................................................... 16 soft start ........................................................................................ 16 noise reduction of the ADP7142 in adjustable mode .............. 17 current limit and thermal overload protection ................. 17 thermal considerations ............................................................ 18 printed circuit board layo ut considerations ............................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 25 rev. prd | page 2 of 25 free datasheet http://
preliminary technical data ADP7142 rev. prd | page 3 of 25 specifications v in = v out +1 v or 2.7 v, whichever is greater, v out = 5v, en= v in , i out = 10 ma, c in = c out = 2.2 f, c ss = 0pf, t a = 25c for typical specifications, t j = ?40c to +125c for minimum/maximum specifications, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input voltage range v in 2.7 40 v operating supply current i gnd i out = 0 a 50 140 a i out = 10 ma 80 200 a i out = 200 ma 180 320 a shutdown current i gnd-sd en = gnd 1.8 a en = gnd, t j = ?40c to +85c 10 a output voltage accuracy output voltage accuracy v out i out = 10 ma C1 +1 % 100 a< i out < 200 ma v in = (vout + 1v) to 40 v C2 +2 % line regulation ?v out /?v in v in = (vout + 1v) to 40 v C0.01 +0.01 %/v load regulation 1 ?v out /?i out i out = 100 a to 200 ma 0.002 0.005 %/ma sense input bias current sense i-bias 100 a< iout < 200 ma v in = (vout + 1v) to 40 v 10 1000 na dropout voltage 2 v dropout i out = 10 ma 30 60 mv i out = 200 ma 200 450 mv start-up time 3 t start-up v out = 5 v 380 s soft-start source current ss i-source ss = gnd 1.2 a current limit threshold 4 i limit 220 400 600 ma thermal shutdown thermal shutdown threshold ts sd t j rising 150 ? c thermal shutdown hysteresis ts sd-hys 15 ? c undervoltage thresholds input voltage rising uvlo rise 2.69 v input voltage falling uvlo fall 2.2 v hysteresis uvlo hys 180 mv en input standby 2.7 v vin 40 v en input logic high en stby-high 1.0 v en input logic low en stby-low 0.4 v en input logic hysteresis en stby-hys 200 mv en input precision 2.7 v vin 40 v en input logic high en high 1.16 1.22 1.28 v en input logic low en low 1.07 1.13 1.18 v en input logic hysteresis en hys 100 mv en input leakage current i en-lkg en = v in or gnd 0.04 1 a en input delay time ti en-dly from en rising from 0v to v in to 0.1v out 80 s output noise out noise 10 hz to 100 khz, all output voltage options 11 vrms power supply rejection ratio psrr 1 mhz, v in = 7v, v out = 5v 50 db 100 khz, v in = 7v, v out = 5v 68 db 10 khz, v in = 7v, v out = 5v 88 db 1 based on an end-point calculation using 100 a and 200 ma loads. see figure 7 for typical load regulation performance for loads less than 1 ma. 2 dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output vol tage. dropout applies only for output voltages above 2.7 v. 3 start-up time is defined as the time between the rising edge of en to out being at 90% of its nominal value. 4 current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 5.0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 v, or 4.5 v. free datasheet http://
ADP7142 preliminary technical data input and output cap acitor, recommended speci fications parameter symbol conditions min typ max unit minimum input and output capacitance 1 c min t a = ?40c to +125c 1.5 f capacitor esr r esr t a = ?40c to +125c 0.001 0.3 1 the minimum input and output capacitance should be greater than 1.5 f over the full range of operating conditions. the full range of operating conditions in the applicati on must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type c apacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo. rev. prd | page 4 of 25 free datasheet http://
preliminary technical data ADP7142 absolute maximum rat ings table 2. parameter rating vin to gnd C 0.3 v to +44 v vout to gnd C 0.3 v to vin en to gnd C 0.3 v to vin sense to gnd C 0.3 v to 6v ss to gnd C 0.3 v to vin or 6v (whichever is less) storage temperature range C 65c to +150c operating junct ion temperature range C 40c to +125c operating ambient temperature range C 40c to +85c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabil ity. thermal data absolute maximum ratings apply individually only, not in combination. the ADP7142 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperat ure limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature ca n exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), a nd the junction - to - ambient t hermal resistance of the pa ckage ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + (p d ja ) junction - to - ambient thermal resistance ( ja ) of the package is based on modeling and calculat ion using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of j a may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in. 3 in. circuit ?board. see jesd51 - 7 and jesd51 - 9 for detailed information on the board construction. jb is the junctio n - to - board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4 - layer board. the jesd51 - 12, guidelines for reporting and using electronic package thermal information , states that thermal c haracterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the to p of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + (p d jb ) see jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja , jc , and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja jc jb unit 6- lead lfcsp 72.1 42.3 47.1 c/w 8- lead soic 52.7 41.5 32.7 c/w 5 - lead tsot 170 n/a 43 c/w esd caution rev. prd | page 5 of 25 free datasheet http://
ADP7142 preliminary technical data pin configuration s and function descrip tions vout vin 1 5 4 3 2 6 top view (not to scale) sense/ adj gnd ss en figure 3 . lfcsp package 1 5 3 2 4 vout en gnd vin sense/ adj figure 4 . tsot package top view (not to scale) vout vin gnd sense/ adj vout en ss vin 1 7 6 5 4 3 2 8 figure 5 . soic package table 4 . pin function descriptions lfcsp mnemonic description 1 vout regulated output voltage. bypass v out to gnd with a 2.2 f or greater capacitor. 2 sense /adj sense input. connect to load. an external resistor divider may also be used to set the output voltage higher than the fixed output voltage 3 gnd ground. 4 en drive en high to turn on the regul ator; drive en low to turn off the regulator. for automatic startup, connect en to vin. 5 ss soft start. a n external capacitor connected to this pin determines the soft - start time. this pin may be left open for a typical 320 s start up time. do not gr ound this pin. 6 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacitor. ep ep exposed pad on the bottom of the package. ep enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the ep connect to the ground plane on the board. soic mnemonic description 1 vout regulated output voltage. bypass vout to gnd with a 2.2 f or greater capacitor. 2 vout regulated output voltage. bypass vout to gnd with a 2.2 f or greater capacito r. 3 sense /adj sense input. connect to load. an external resistor divider may also be used to set the output voltage higher than the fixed output voltage 4 gnd ground. 5 en drive en high to turn on the regulator; drive en low to turn off the regulator . for automatic startup, connect en to vin. 6 ss soft start. a n external capacitor connected to this pin determines the soft - start time. this pin may be left open for a typical 320 s start up time. do not ground this pin. 7 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacitor. rev. prd | page 6 of 25 free datasheet http://
preliminary technical data ADP7142 soic mnemonic description 8 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacito r. ep ep exposed pad on the bottom of the package. ep enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the ep connect to the ground plane on the board. tsot mnemonic description 1 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacitor. 2 gnd ground. 3 en drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. 4 sense /adj sense input. connect to load. an external resistor divider may also be used to set the output voltage higher than the fixed output voltage 5 vout regulated output voltage. bypass vout to gnd with a 2.2 f or greater capacitor. rev. prd | page 7 of 25 free datasheet http://
ADP7142 preliminary technical data typical performance characteristics v in = 7. 5 v, v out = 5 v , i out = 1 0 ma , c in = c out = 2.2 f , t a = 25c, unless otherwise noted . 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 -40'c -5'c 25'c 85'c 125'c tj ('c) vout (v) load = 100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 6 . output voltage vs. junction temperature 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 0.1 1 10 100 1000 iload (ma) vout (v) figure 7 . output voltage vs. load current 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 vin (v) vout (v) load=100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 8 . output voltage vs. input voltage 0 50 100 150 200 250 300 -40'c -5'c 25'c 85'c 125'c tj ('c) ground current (ua) load=100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 9 . ground current vs. junction temperature 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 100 1000 iload (ma) ground current (ua) figure 10 . ground current vs. load current 0 50 100 150 200 250 300 5 10 15 20 25 30 35 40 vin (v) ground current (ua) load=100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 11 . ground current vs. in put voltage rev. prd | page 8 of 25 free datasheet http://
preliminary technical data ADP7142 shutdown current vs temp (different vins) 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 -50 -25 0 25 50 75 100 125 temp ('c) shutdown current (ua) 2.7 3 5 6 10 40 figure 12 . shutdown current vs. temperature at various input voltages temp=25'c 0 50 100 150 200 250 1 10 100 1000 load (ma) dropout (mv) figure 13 . dropout voltage vs. load current , v out = 5 v 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 4.80 5.00 5.20 5.40 5.60 vin (v) vout (v) vdrop 5ma vdrop 10ma vdrop 50ma vdrop 100ma vdrop 150ma vdrop 200ma figure 14 . output voltage vs. i nput voltage (in dropout) , v out = 5 v 0 100 200 300 400 500 600 700 800 900 1000 4.80 5.00 5.20 5.40 5.60 vin (v) ground current (au) ignd 5ma ignd 10ma ignd 50ma ignd 100ma ignd 150ma ignd 200ma figure 15 . ground current vs. input voltage (in dropout) , v out = 5 v 3.25 3.27 3.29 3.31 3.33 3.35 -40'c -5'c 25'c 85'c 125'c tj ('c) vout (v) load = 100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 16 . output voltage vs. junction temperature, v out = 3.3 v 3.25 3.27 3.29 3.31 3.33 3.35 0.1 1 10 100 1000 iload (ma) vout (v) figure 17 . output voltage vs. load current, v out = 3.3 v rev. prd | page 9 of 25 free datasheet http://
ADP7142 preliminary technical data 3.25 3.27 3.29 3.31 3.33 3.35 0 5 10 15 20 25 30 35 40 vin (v) vout (v) load=100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 18 . output voltage vs. input voltage, v out = 3.3 v 0 50 100 150 200 250 300 -40'c -5'c 25'c 85'c 125'c tj ('c) ground current (ua) load=100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 19 . ground current vs. junction temperature, v out = 3.3 v 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 100 1000 iload (ma) ground current (ua) figure 20 . ground current vs. load current, v out = 3.3 v 0 50 100 150 200 250 300 0 10 20 30 40 vin (v) ground current (ua) load=100ua load=1ma load=10ma load=50ma load=100ma load=200ma figure 21 . ground current vs. input voltage, v out = 3.3 v temp=25'c 0 50 100 150 200 250 300 1 10 100 1000 load (ma) dropout (mv) figure 22 . dropout voltage vs. load current , v out = 3.3 v 2.8 2.9 3 3.1 3.2 3.3 3.4 3.1 3.3 3.5 3.7 3.9 vin (v) vout (v) vdrop 5ma vdrop 10ma vdrop 50ma vdrop 100ma vdrop 150ma vdrop 200ma figu re 23 . output voltage vs. input voltage (in dropout) , v out = 3.3 v rev. prd | page 10 of 25 free datasheet http://
preliminary technical data ADP7142 0 100 200 300 400 500 600 700 3.1 3.3 3.5 3.7 3.9 vin (v) ground current (au) ignd 5ma ignd 10ma ignd 50ma ignd 100ma ignd 150ma ignd 200ma figure 24 . ground current vs. input voltage (in dropout) , v out = 3.3 v 1 1.1 1.2 1.3 1.4 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 soft start current (ua) temperature (degc) ADP7142 1.8v soft start current vs temperature 2.7v 5v 10v 20v 40v figure 25 . soft start current v s. temperature, different input voltage, v out = 5 v -120 -100 -80 -60 -40 -20 0 10 100 1000 10000 100000 1000000 10000000 psrr (db) frequency (hz) ADP7142 lfcsp psrr, 3.3v/200ma different headroom 3v 2v 1.6v 1.4v 1.2v 1v 800mv 700mv 600mv 500mv figure 26 . power supply rejection ratio vs. frequency, v out = 3.3 v, various headroom voltage -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.8 1.2 1.6 2 2.4 2.8 psrr (db) frequency (hz) ADP7142 lfcsp psrr vs headroom voltage 3.3v/200ma different frequency 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 27 . power supply rejection ratio vs. headroom , v out = 3.3 v, different frequencies -120 -100 -80 -60 -40 -20 0 10 100 1000 10000 100000 1000000 10000000 psrr (db) frequency (hz) ADP7142 lfcsp psrr, 5v/200ma different headroom 3v 2v 1.6v 1.4v 1.2v 1v 800mv 700mv 600mv 500mv figure 28 . power supply rejection ratio vs. frequency, v out = 5 v, various headroom voltage -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.8 1.2 1.6 2 2.4 2.8 psrr (db) frequency (hz) ADP7142 lfcsp psrr vs headroom voltage 5v/200ma different frequency 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 29 . power supply rejection ratio vs. headroom , v out = 5 v, dif ferent frequencies rev. prd | page 11 of 25 free datasheet http://
ADP7142 preliminary technical data 0 4 8 12 16 20 1 10 100 1000 noise (uvrms) load current (ma) adm7142 rms noise vs load current 10-100khz 100-100khz figure 30 . rms output noise vs. load curren t 1 10 100 1000 10000 1 10 100 1000 10000 100000 1000000 10000000 nv/rt - hz frequency (hz) adm7142 5v c out = 2.2uf noise spectral density nsd figure 31 . output noise spectral density, i load = 10 ma ADP7142 nsd vs frequency different loads v out = 5v 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 1000000 10000000 frequency nsd (nv/rt-hz 100ua 1ma 10ma 100ma 200ma figure 32 . output noise spectral density vs i loa d 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 1000000 10000000 nv/rt - hz frequency (hz) adm7142 c out = 2.2uf noise spectral density 1.8v 3.3v 5v figure 33 . output noise spectral density, different output voltages figure 34 . load transient response, i load = 1 ma to 2 00 ma , v out = 5 v, v in = 7 v , ch1 load current, ch2 v out figure 35 . line transient response , i load = 2 00 ma, v out = 5 v , ch1 v in , ch2 v out rev. prd | page 12 of 25 free datasheet http://
preliminary technical data ADP7142 figure 36 . load transient response, i load = 1 ma to 2 00 ma, v out = 1.8 v, v in = 3 v , ch1 load current, ch2 v out figure 37 . line transient response, i load = 200 ma, v out = 1.8 v , ch1 v in , ch2 v out rev. prd | page 13 of 25 free datasheet http://
ADP7142 preliminary technical data theory of operation the ADP7142 is a low quiescent current, low - dropout linear regulat or that operates from 2 . 7 v to 4 0 v and provide s up to 2 00 ma of output current. drawing a low 250 a of quiescent current (typical) at full load makes the ADP7142 ideal for portable equipment. typical shutdown current consumption is 3 a at room temperature. optimized for use with small 2.2 f ceramic capacitors, the ADP7142 provides excellent transient performance. sense / adj gnd vout shutdown + - vin en reference short circuit , thermal protect figure 38 . internal block diagram internall y, the ADP7142 consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is controlled by the error amplif ier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the ADP7142 is available in 16 fixed output voltage options, ranging from 1. 2 v to 5 v . the ADP7142 architecture allows any fixed output voltage to be set to a higher voltage with an external voltage divider. for example, a fixed 5v output adp71 42 can be set to a 6v output according to the following equation: v out = 5 v(1 + r1 / r2 ) r1 2k r2 10k vout=6v vin=7v vout vin gnd en 2.2uf cin 2.2uf cout on off sense/adj 1nf css ss figure 39 . typical adjustable output voltage application schematic the value of r2 should be less than 200 k to minimize errors in the outp ut voltage caused by the sense/ adj pin input current. for example, wh en r1 and r2 each equal 200 k and the default output voltage is 1.2v, the adjusted output voltage is 2.44 v. the output voltage error introduced by the sense/ adj pin input current is 1 mv or 0.0 4 %, assuming a typical sense/ adj pin input current of 10 na at 25c. the ADP7142 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on, wh en en is low, vout turns off. for automatic startup, en can be tied to vin. rev. prd | page 14 of 25 free datasheet http://
preliminary technical data ADP7142 applications informa tion capacitor selection output capacitor the ADP7142 is designed for operation with small, space - saving ceram ic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 2.2 f capacitan ce with an esr of 0.3 ? or less is recommended to ensure the stability of the ADP7142 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the t ransient response of the ADP7142 to large changes in load current. figure 62 shows the transient responses for an output capacitance value of 2.2 f. figure 40 . output transient response, v out = 5 v, c out = 2.2 f input bypass capacitor connecting a 2.2 f capacitor from vin to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedan ce are encountered. if greater than 2.2 f of output capacitance is required, the input capacitor should be increased to match it. input and output capacitor properties any good quality ceramic capacitors can be used with the ADP7142 , as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufac - tured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must hav e a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v to 100 v are recommended. y5v and z5u dielectrics are not recommended, due to the ir poor temperature and dc bias characteristics. figure 63 depicts the capacitance vs. voltage bias characteristic of an 0 8 0 5 , 2.2 f , 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capa citor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature varia tion of the x5r dielectric is ~ 15% over the ?40c to +85 c temperature range and is not a function of packa ge or voltage rating. capacitance vs dc bias 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 dc bias voltage capacitance (uf) capacitance figure 41 . capacitance vs. voltage characteristic use equation 1 to determine the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (t empco) over ?40 c to +85 c is assumed to be 15% for an x5r dielectric . the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 2.09 f at 5 v, as shown in figure 63. substituting these values in equation 1 yields c eff = 2. 09 f (1 ? 0.15) (1 ? 0.1) = 1.59 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temper - ature and tolerance at the chosen output voltage. to guarantee the performance of the ADP7142 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. rev. prd | page 15 of 25 free datasheet http://
ADP7142 preliminary t echnical data programable precision enable the ADP7142 uses the en pin to enable and disable the vout pin under normal operating conditions. as shown in figure 42 , when a rising voltage on en crosses the upper threshold, nominally 1.2v, vout turns on. when a falling voltage on en crosses the lower threshold, nominally 1.1v, vout turns off. the hysteresis of the en threshold is approximately 100mv . 0 0.5 1 1.5 2 2.5 3 3.5 1.05 1.1 1.15 1.2 1.25 1.3 -40c 25c 125c figure 42 . typical vout response to en pin operation the upper and lower thresholds are user programmable and can be set higher than the nominal 1.2v threshold by using two resistors. the resistance values, r en 1 and r en 2 can be determined from: r en 2 = nominally 10k to 100k ren1 = r en2 ( v in - 1.2v)/1.2v where: v in is the desired turn - on voltage. the h ysteresis voltage will increased by the factor (ren1+ren2) /ren1 . for the example shown in figure 43 , the e nable threshold is 3.6 v with a hysteresis of 3 00 m v. vout=6v vin=8v vout vin gnd sense/ adj en 2.2uf cin 2.2uf cout ren1 200k ren2 100k on off rfb2 100k rfb1 10k figure 43 . typical en pin voltage divider figure 64 shows the typical hysteresis of the en pin. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the ADP7142 uses an internal soft - start (ss pin open) to limit the inrush current when the output is enabled. the start - up time for the 3.3 v option is approximately 320 s from the time the en active threshold is crossed to when the output reaches 90% of its final value. as shown in figure 44 , the start - up time is dependent on the output voltage setting. 0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ven 1.8v 3.3v 5v figure 44 . ty pical start - up behavior soft start a n external capacitor connected to th e ss pin determines the soft - start time. this pin may be left open for a typical 320 s start up time. do not ground this pin. when an external soft start capacitor is used, the sof t start time is determined by the following equation: ss time (s) = 320 s + 0.6 c ss where c ss is in farards rev. prd | page 16 of 25 free datasheet http://
preliminary technical data ADP7142 0 0.5 1 1.5 2 2.5 3 3.5 0 1 2 3 4 5 6 7 8 9 10 output voltage (v) time (ms) soft start behavior different ss capacitance ven no ss cap 1nf 2nf 4.7nf 6.8nf 10nf figure 45 . ty pical soft start behavi or, different c ss n oise r eduction of the ADP7142 in adjustable mode the ultralow output noise of the ADP7142 is achieved by keeping the ldo error amplifier in unity gain and setting the reference voltage equal to the output voltage. this archi tecture does not work for an adjustable output voltage ldo in the conventional sense. however, t he ADP7142 architecture allows any fixed output voltage to be set to a higher voltage with an external voltage divider. for example, a fixed 5v output adp714 2 can be set to a 6v output according to the following equation: v out = 5 v(1 + r1 / r2 ) the disadvantage using the adp1742 in this manner i s that the output voltage noise is proportional to the output voltage. therefore, it is best to choose a fixed output voltage that is close to the target voltage to minimize the increase in output noise. the adjustable ldo circuit may be modified to reduce the output voltage noise to levels close to that of the fixed output a dp7142 . the circuit shown in figure 46 adds two additional components to the output voltage setting resistor divider. c nr and r nr are added in parallel with r fb1 to reduce the ac gain of the error amplifier. r nr is chosen to be s mall with respect to r fb2 . if r nr is 1% to 10 % of the value of r fb 2 , t he minimum ac gain of the error amplifier is approxi mately 0.1 to 0. 8 db. the actual gain is determined by the parallel combination of r nr and r fb1 . this ensures that the error amplifie r always operates at slightly greater than unity gain. c nr is chosen by setting the reactance of c nr equal to r fb1 ? r nr at a frequency between 1 hz and 5 0 hz. this sets the frequency where the ac gain of the error amplifier is 3 db down from its dc gain . vout = 10 v vin = 12 v vout vin gnd sense / adj en / uvlo 2 . 2 uf cin rfb 1 100 k rfb 2 100 k 2 . 2 uf cout 200 k 100 k on off 1 uf cnr rnr 10 k figure 46 . noise reduction modification the noise of the adjustable ldo is can be found by using the formula below assuming the noise of a fixed output ldo is approximately 1 1 v. noise = 1 1 v ( r par +r fb2 )/r fb2 where: r par = pa rallel combination of r fb 1 and r nr based on the component values shown in figure 46 , the ADP7142 has the following characteristics: ? dc gain of 2 ( 6 db) ? 3 db roll off f requency of 1. 59 hz ? high frequency ac gain of 1.09 ( 0 .7 5 db) ? noise reduction factor of 1.83 ( 5.25 db) ? rms noise of the adjustable ldo without noise reduction of 2 2 v rms ? rms noise of the adjustable ldo with noise reduc - tion (assuming 1 1 v rms for fixed voltage opti on) of 1 2 v rms current limit and th ermal overload protection the ADP7142 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the ADP7142 is designed to current limit when the output load reaches 4 00 ma (typical). when the output load exceeds 4 00 ma, the output voltage is reduced to maintain a constant current limit. thermal overload pro tection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 150c, the output is t urned off, reducing the output current to zero. when the junction temperature drops below 135c, the output is turned on again, and output current is restored to its operating value. consider the case where a hard short from vout to ground occurs. at first , the ADP7142 current limits, so that only 4 00 ma is co nducted into the short. if self heating of the junction is great enough to cause its temperature to rise above 150c, thermal s hutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 4 00 ma into the short, again causing the junction temperature rev. prd | page 17 of 25 free datasheet http://
ADP7142 preliminary t echnical data to rise above 150c. this thermal oscillation be tween 135c and 150c causes a current oscillation between 4 00 ma and 0 ma that continues as long as the short remains at the outpu t. current and thermal limit protections are intended to protect the device against accidental overload conditions. for relia ble operation, device power dissipation must be externally limited so the junction temperature does not exceed 125c. thermal consideratio ns in applications with low input - to - output voltage differential, the ad p7142 does not dissipate much heat. however, in applications with high ambient temperature and/or high input voltage , the heat dissipated in the package may become large enough that it cause s the junction temperature of the die to exceed the maximum jun ction temperature of 125c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temper ature has decreased below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera - ture rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the ADP7142 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user must b e aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature , power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 5 shows typical ja v alues of the 8 - lead soic and 6 - l ead lfcsp and 5 - lead tsot package s for various pcb copper sizes. table 6 shows the typical jb values of the 8 - lead soic , 6 - lead lfcsp , and 5 - lead tsot . table 5 . typical ja values copper size (mm 2 ) ja (c/w) lfcsp soi c tsot 25 1 182.8 n/a n/a 50 n/a 181.4 152 100 142.6 145.4 146 500 83.9 89.3 131 1000 71.7 77.5 n/a 6400 57.4 63.2 n/a 1 device soldered to minimum size pin traces. table 6 . typical jb values model jb (c/w) lfcsp 24 soi c 38.8 tsot 43 the junction temperature of the ADP7142 is calculated from the following equation: t j = t a + (p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature , input - to - output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 47 to figure 55 show junction temperature calculations for different ambient temperatures, po wer dissipation, and areas of pcb copper. 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0 105.0 115.0 125.0 135.0 145.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 total pow er dissipation (w) junction temperature o c 6400 mm sq 500 mm sq 25 mm sq tjmax figure 47 . lfcsp, t a = 25c rev. prd | page 18 of 25 free datasheet http://
preliminary technical data ADP7142 50.0 60.0 70.0 80.0 90.0 100.0 110.0 120.0 130.0 140.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 total pow er dissipation (w) junction temperature o c 6400 mm sq 500 mm sq 25 mm sq tjmax figure 48 . lfcsp, t a = 50c 50.0 60.0 70.0 80.0 90.0 100.0 110.0 120.0 130.0 140.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 total pow er dissipation (w) junction temperature o c 6400 mm sq 500 mm sq 25 mm sq tjmax figure 49 . lfcsp, t a = 85c 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0 105.0 115.0 125.0 135.0 145.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 total pow er dissipation (w) junction temperature o c 6400 mm sq 500 mm sq 50 mm sq tjmax figure 50 . soic , t a = 25c 50.0 60.0 70.0 80.0 90.0 100.0 110.0 120.0 130.0 140.0 0 0.2 0.4 0.6 0.8 1 1.2 total pow er dissipation (w) junction temperature o c 6400 mm sq 500 mm sq 50 mm sq tjmax figure 51 . soic, t a = 50c 65.0 75.0 85.0 95.0 105.0 115.0 125.0 135.0 145.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 total pow er dissipation (w) junction temperature o c 6400 mm sq 500 mm sq 50 mm sq tjmax figure 52 . soic, t a = 85c 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0 105.0 115.0 125.0 135.0 145.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 total pow er dissipation (w) junction temperature o c 500 mm sq 100 mm sq 50 mm sq tjmax figure 53 . tsot , t a = 25c rev. prd | page 19 of 25 free datasheet http://
ADP7142 preliminary t echnical data 50.0 60.0 70.0 80.0 90.0 100.0 110.0 120.0 130.0 140.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 total pow er dissipation (w) junction temperature o c 500 mm sq 100 mm sq 50 mm sq tjmax figure 54 . tso t , t a = 50c 65.0 75.0 85.0 95.0 105.0 115.0 125.0 135.0 145.0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 total pow er dissipation (w) junction temperature o c 500 mm sq 100 mm sq 50 mm sq tjmax figure 55 . tso t , t a = 85c rev. prd | page 20 of 25 free datasheet http://
preliminary technical data ADP7142 in the case where the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temperature rise (see figure 56, figure 57 , and figure 58 ). maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + (p d jb ) (5) the typical value of jb is 24 c/w for the 8 - lead lfcsp package , 3 8.8 c/w for the 8 - lead soic package and 4 3c/w for the 5 - lead t sot package. 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 total power dissipation (w) junction temperature (t j ) tb= 25c tb= 50c tb= 65c tb= 85c tjmax figure 56 . lfcsp 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 total power dissipation (w) junction temperature (t j ) tb= 25c tb= 50c tb= 65c tb= 85c tjmax figure 57 . soic 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 total power dissipation (w) junction temperature (t j ) tb= 25c tb= 50c tb= 65c tb= 85c tjmax figure 58 . tsot rev. prd | page 21 of 25 free datasheet http://
ADP7142 preliminary t echnical data printed circuit b oard layout considerations heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7142 . however, as listed in table 5 , a point of diminishing returns is eventually reached, beyond which an increas e in the co pper siz e does not yield significant heat dissipation benefits . place t he input capacitor as close as possible to the v in and gnd pins. place t he output capacitor as close as possible to the v out and gnd pins . use of 0805 or 120 6 size capacitors and resistors achi eve s the smallest possible footprint solution on boards where area is limited . figure 59 . example lfcsp pcb layout figure 60 . example soic pcb layout figure 61 . example tsot p cb layout rev. prd | page 22 of 2 5 free datasheet http://
preliminary technical data ADP7142 outline dimensions 1.70 1.60 1.50 0.425 0.350 0.275 t op view 6 1 4 3 0.35 0.30 0.25 b o t t o m v i e w pin 1 index area sea ting plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.05 max 0.02 nom 2.00 bsc sq 0.65 bsc e x p o s e d p a d p i n 1 i n d i c a t o r ( r 0 . 1 5 ) 05-04-2010-a figure 62 . 6 - pin leadframe chip scale package [lfcsp] (cp6 - 3) dimensions shown in millimeters compliant t o jedec s t andards ms-012-a a 06-02-20 1 1-b 1.27 0.40 1.75 1.35 2.29 2.29 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarit y 0.10 1.04 ref 8 1 4 5 1.27 bsc se a ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 0.51 0.31 1.65 1.25 figure 63 . 8 - lead standard small outline package, with exposed pad [soic_n_e p] narrow body (rd - 8 - 1 ) dimensions shown in millimeters rev. prd | page 23 of 25 free datasheet http://
ADP7142 preliminary technical data * compliant to jedec standards mo-193-ab with the exception of package height and thickness. pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max seating plane * 1.00 max * 0.90 0.87 0.84 2.90 bsc 5 4 1 2 3 figure 64 . 5 - lead thin small outline transistor package [tsot] (uj - 5) dimensions shown in millimeters rev. prd | page 24 of 25 free datasheet http://
preliminary technical data ADP7142 ordering guide model 1 temperature range output voltage (v) 2 , 3 package description package option branding ADP7142acpzn -r2 ? 40c to +125c adjustable 6- lead lfcsp_wd cp -6-3 lp4 ADP7142 acpz n -r7 ? 40c to +125c adjustable 6- lead lfcsp_wd cp -6-3 lp4 ADP7142 acpz n -1.8-r2 ? 40c to +125c 1.8 6- lead lfcsp_wd cp -6-3 lp5 ADP7142 acpz n -1.8-r7 ? 40c to +125c 1.8 6- lead lfcsp_wd cp -6-3 lp5 ADP7142 acpz n -2.5-r2 ? 40c to +125c 2.5 6- lead lfcsp_wd cp -6-3 lp6 ADP7142 acpz n - 2.5 - r7 ? 40c to +125c 2.5 6 - lead lfcsp_wd cp - 6 - 3 lp6 ADP7142 acpz n -3.3-r2 ? 40c to +125c 3.3 6- lead lfcsp _wd cp -6-3 lp7 ADP7142 acpz n -3.3-r7 ? 40c to +125c 3.3 6- lead lfcsp_wd cp -6-3 lp7 ADP7142 acpz n -5.0-r2 ? 40c to +125c 5 6- lead lfcsp_wd cp -6-3 lp8 ADP7142 acpz n -5.0-r7 ? 40c to +125c 5 6- lead lfcsp_wd cp -6-3 lp8 ADP7142 ardz - r7 ? 40c to +125c adjustabl e 8- lead soic_n_ep rd -8-2 ADP7142ardz - 1.8 ? 40c to +125c 1.8 8- lead soic_n_ep rd -8-2 ADP7142 ardz - 1.8-r7 ? 40c to +125c 1.8 8- lead soic_n_ep rd -8-2 ADP7142 ardz - 2.5 ? 40c to +125c 2.5 8- lead soic_n_ep rd -8-2 ADP7142 ardz - 2.5-r7 ? 40c to +125c 2.5 8- lead soic_n_ep rd -8-2 ADP7142 ardz - 3.3 ? 40c to +125c 3.3 8- lead soic_n_ep rd -8-2 ADP7142 ardz - 3.3 - r7 ? 40c to +125c 3.3 8 - lead soic_n_ep rd - 8 - 2 ADP7142 ardz - 5.0 ? 40c to +125c 5 8- lead soic_n_ep rd -8-2 ADP7142 ardz - 5.0-r7 ? 40c to +125c 5 8- lead soic_n_ep rd -8-2 ADP7142 a ujz - r2 ? 40c to +125c adjustable 5- lead tsot uj -5 lp4 ADP7142 a uj z - r7 ? 40c to +125c adjustable 5- lead tsot uj -5 lp4 ADP7142aujz - 1.8 -r2 ? 40c to +125c 1.8 5- lead tsot uj -5 lp5 ADP7142auj z - 1.8 -r7 ? 40c to +125c 1.8 5- lead t sot uj -5 lp5 ADP7142aujz - 2.5 -r2 ? 40c to +125c 2.5 5- lead tsot uj -5 lp6 ADP7142auj z - 2.5 -r7 ? 40c to +125c 2.5 5- lead tsot uj -5 lp6 ADP7142aujz - 3.3 -r2 ? 40c to +125c 3.3 5- lead tsot uj -5 lp7 ADP7142auj z - 3.3 -r7 ? 40c to +125c 3.3 5- lead tsot uj -5 lp7 ADP7142aujz - 5.0 - r2 ? 40c to +125c 5 5 - lead tsot uj - 5 lp8 ADP7142auj z - 5.0 -r7 ? 40c to +125c 5 5- lead tsot uj -5 lp8 ADP7142uj - evalz 3.3 tsot evaluation board ADP7142 cp - evalz 3.3 lfcsp evaluation board ADP7142 rd - evalz 3.3 soic evaluation board 1 z = rohs compliant part. 2 for additional voltage options, contact a local analog devices, inc., sales or distribution representative . 3 the evaluation boards are preconfigured with a 3.3 v adp714 2 . ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr11848 - 0 - 2/14(prd) rev. prd | page 25 of 25 free datasheet http://

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